As society's dependency on computer systems and computer-controlled devices grows, it becomes increasingly important to verify the integrity of the components which make up such systems. One method of testing the integrity of a logic component consists of transmitting a series of random numbers into the input of the logic module of the component, accumulating the outputs generated by the module in a data compression register (DCR), and, when the entire series of numbers has been processed by the logic module, comparing the output signature of the DCR with a predetermined correct signature. If the DCR output signature matches the correct signature, then the logic component is functioning properly; otherwise, it is faulty.
Consequently, logic component architectures have been developed which provide built-in self-testing (BIST). Such architectures contain, in addition to a logic module, the hardware required to test the module (i.e. a pseudo random number generator (PRNG) and a DCR). During normal operation, the logic module receives data from normal inputs and transmits data to normal outputs. During testing, the logic module receives input from the PRNG and transmits its output to the DCR.
One disadvantage of current BIST architectures is that the testing logic embodied therein consumes power as it is driven by the system clock whether or not the logic module is being tested. Such unnecessary power consumption makes BIST-equipped architectures generally less energy efficient than architectures without testing logic. For example, for one circuit comprising six BIST-equipped logic modules, it has been observed that testing logic adds a power load of approximately 2.5 pF which, at each clock cycle, consumes about 23 mW of dynamic power.
It is therefore clearly desirable to provide a BIST architecture which disables testing logic when the logic module is not being tested. It is further desirable to provide means for enabling the testing logic for testing operations that will not accidentally enable the testing logic during normal operation.